Exemplary embodiments of the present invention relate to an accumulator and a data weighted average device including the same, and more particularly, to an accumulator for reducing nonlinearity of a data converter and a data weighted average device including the accumulator.
Nonlinearity of an output signal is one of the important design factors in a data converter. The nonlinearity largely reduces a signal-to-noise and distortion ratio (SNDR) of the output signal.
Generally, a digital-to-analog converter (hereinafter, referred to as ‘DAC’) affects linearity of the output element due to several factors. Among these factors, various types of mismatches of each unit component of the DAC have a serious effect on nonlinearity. In actual implementation, a data weighted average (DWA) method has been applied in order to improve the nonlinearity due to the mismatches.
An object of the data weighted average method changes a distribution of paths switching each unit component to randomly show a mismatch effect.
FIG. 1 is a block diagram of an ADC to which the DAC is applied.
FIG. 1 illustrates a general multi-bit delta-signal analog-to-digital converter (hereinafter, referred to as ‘ADC’) 10 that converts an analog input signal As_in into a digital output signal DS_out.
The multi-bit delta-sigma ADC 10 includes an integrator and adder 11, a multi-level quantizer 12, a DAC 13, a data weighted average unit 14, and an output decoder (DEC) 15.
The multi-bit delta-sigma ADC 10 is a data converter that has been mainly used for applications requiring high bit resolution. When the multi-bit delta-sigma ADC 10 has high resolution or wide bandwidth, the multi-bit quantizer 12 is used and the multi-bit DAC 13 is required since the output signal is transmitted to an input end through a feedback. As described above, the data weighted average method is required due to the use of the DAC 13.
In particular, the multi-bit delta-sigma ADC 10 having a feedback loop shows initial noise of an input on an output as it is, and therefore, the linearity of the signal fed back to the DAC 13 is considerably important.
FIGS. 2A and 2B are diagrams for describing a configuration and an operation principle of a general data weighted average unit used in the DAC.
Referring to FIG. 2A, the data weighted average unit includes a log shifter 21 that converts a path through which an input digital signal D_in of m bits is transmitted as an output by a control signal of k bits and a counter 22 that generates the control signal of k bits.
An output signal D_out of n bits controls the DAC units based on a configuration block, as appearing in an operation sample illustrated in FIG. 2B. When the DAC unit is large in an order of 2-1-1-2-3-2-3-2- . . . , the output from the data weighted average unit reduces the nonlinearity occurring from the DAC by being sequentially turned-on without repeatedly turning-on the same cell.
Here, when the DAC unit is 2n, the counter 22 of the data weighted average unit implements a circuit counting 2n, which can be easily implemented using an N-bit counter or an N-bit accumulator.
However, when counting 2n, a bit width of the DAC is implemented to meet 2n and therefore and therefore, when intending to implement the required optimal bit width of the DAC, there is a problem in that the bit width cannot be implemented using the N-bit counter or the N-bit accumulator.
As the related art, there is KR Patent Laid-Open No. 2008-0020096 (Publication on Mar. 5, 2008, Title of the Invention: Multi-bit Data Converter Using Data Weighted Averaging).
The above-mentioned technical configuration is a background art for helping understanding of the present invention and does not mean related arts well known in a technical field to which the present invention pertains.